Design Using HDL
The vast majority of modern digital circuit-design revolves around an HDL-description of the desired circuit, device, or subsystem.

Most designs begin on traditional pencil and paper, as written set of requirements or a high-level architectural diagram. The process of writing the HDL-description is highly dependent on the designer's background and the circuit's nature. The HDL is merely the 'capture language' -- designers often begin with a high-level algorithmic description (such as MATLAB or a C++ mathematical model.) Control and decision structures are often prototyped in flowchart applications, or entered in a state-diagram editor. Designers even use scripting-languages (such as PERL) to auto-generate repetitive circuit-structures in the HDL language. Advanced text-editors (such as EMACS) offer an editor template to auto-indent, color-highlight syntax keywords, and macro-expand entity/architecture/signal declaration.

As the design's implementation is fleshed out, the HDL-code invariably must undergo code review (i.e. auditing.) In preparation for synthesis, the HDL-description is subject to an array of automated checkers. The checkers enforce standardized-code guidelines (to identify ambiguous code-constructs before they can cause mis-interpretation by downstream synthesis) and check for common logical-coding errors (such as dangling ports or shorted outputs.)

In industry parlance, HDL-design generally ends at the synthesis stage. Once the synthesis-tool has mapped the HDL-description into a gate-netlist, the netlist is passed off to the 'back-end' stage. Depending on the physical technology (FPGA vs ASIC gate-array vs ASIC standard-cell), HDLs may or may not play a significant role in the back-end flow. In general, as the design-flow progresses toward a physically realizeable form, the design-database becomes progressively more laden with technology-specific information, which cannot be stored in a generic HDL-description. The end result is a silicon chip that would be manufactured in a fab.