Hardware Description Language:-
In electronics, a hardware description language or HDL is any language from a class of computer languages for formal description of electronic circuits. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation.

A Hardware Description Language (HDL) is a standard text-based expression of the temporal behaviour and/or (spatial) circuit structure of an electronic system. In contrast to a software programming language, an HDL's syntax and semantics include explicit notations for expressing time and concurrency which are the primary attributes of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as netlist languages.

HDLs are used to write executable specifications of some piece of hardware. A simulation program, designed to implement the underlying semantics of the language statements, coupled with simulating the progress of time, provides the hardware designer with the ability to model a piece of hardware before it is created physically. It is this executability that gives the illusion of HDLs being a programming language. Simulators capable of supporting discrete event (digital), and continuous time (It is certainly possible to represent hardware semantics using traditional programming languages such as C++ (and augmented with extensive and unwieldy class libraries.) However, the C++ language does not include any capability for expressing time explicitly and consequently is not a proper hardware description language.

Using the proper subset of virtually any (hardware description or software programming) language, a software program called a synthesizer can infer hardware logic operations from the language statements and produce an equivalent netlist of generic hardware primitives to implement the specified behaviour. This typically (as of 2004) requires the synthesizer to ignore the expression of any timing constructs in the text. The ability to have a synthesizable subset of the language does not itself make a hardware description language.

Designing a system in HDL is generally much harder and more time consuming than writing a program that would do the same thing using a programming language like C. Consequently, there has been much work done on automatic conversion of C code into HDL, but this has not reached a high level of commercial success as of 2004.

History
The first hardware description languages have been ISP developed at Carnegie Mellon University, and KARL developed at University of Kaiserslautern, both around 1977. ISP was, however, more like a software programming language used to describe relations between the inputs and the outputs of the design. Therefore, it could be used to simulate the design, but not to synthesize it. But KARL has also included design calculus language features supporting VLSI chip floorplanning and Structured hardware design, also the basis of KARL's interactive graphic sister language ABL, having been implemented in the early 1980ies as the ABLED graphic VLSI design editor, by the telecommunication research center CSELT at Torino, Italy. Around the mid 80ies a VLSI design framework has been implemnted around KARL and ABL by an international consortium funded by the commission of the European Union (chapter in [1]). In 1983 Data-I/O introduced ABEL. It was targeted for describing programmable logical devices and was basically used to design finite state machines.

The first modern HDL, Verilog, was introduced by Gateway Design Automation in 1985. Cadence Design Systems later acquired the rights to Verilog-XL, the HDL-simulator which would become the de-facto standard (of Verilog simulators) for the next decade. In 1987, a request from the U.S. Department of Defense led to the development of VHDL (Very High Speed Integrated Circuit Hardware Description Language.) Initially, Verilog and VHDL were used to document and simulate circuit-designs already captured and described in another form (such as a schematic file.) HDL-simulation enabled engineers to work at a higher level of abstraction than simulation at the schematic-level, and thus increased design capacity from hundreds of transistor to thousands.

Design Using HDL
The vast majority of modern digital circuit-design revolves around an HDL-description of the desired circuit, device, or subsystem.

Most designs begin on traditional pencil and paper, as written set of requirements or a high-level architectural diagram. The process of writing the HDL-description is highly dependent on the designer's background and the circuit's nature. The HDL is merely the 'capture language' -- designers often begin with a high-level algorithmic description (such as MATLAB or a C++ mathematical model.) Control and decision structures are often prototyped in flowchart applications, or entered in a state-diagram editor. Designers even use scripting-languages (such as PERL) to auto-generate repetitive circuit-structures in the HDL language. Advanced text-editors (such as EMACS) offer an editor template to auto-indent, color-highlight syntax keywords, and macro-expand entity/architecture/signal declaration.

As the design's implementation is fleshed out, the HDL-code invariably must undergo code review (i.e. auditing.) In preparation for synthesis, the HDL-description is subject to an array of automated checkers. The checkers enforce standardized-code guidelines (to identify ambiguous code-constructs before they can cause mis-interpretation by downstream synthesis) and check for common logical-coding errors (such as dangling ports or shorted outputs.)

In industry parlance, HDL-design generally ends at the synthesis stage. Once the synthesis-tool has mapped the HDL-description into a gate-netlist, the netlist is passed off to the 'back-end' stage. Depending on the physical technology (FPGA vs ASIC gate-array vs ASIC standard-cell), HDLs may or may not play a significant role in the back-end flow. In general, as the design-flow progresses toward a physically realizeable form, the design-database becomes progressively more laden with technology-specific information, which cannot be stored in a generic HDL-description. The end result is a silicon chip that would be manufactured in a fab.